1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a power supply, and in particular to a semiconductor integrated circuit driving an external FET and a power supply incorporating the same.
2. Description of the Background Art
FET driving circuits for driving an external FET (Field Effect Transistor) have been developed. For example, a driving circuit controlling switching of a transistor is disclosed in Japanese Patent Laying-Open Nos. 2000-201475, 2004-088245, and 2003-235251 (Patent Documents 1-3).
Such a conventional driving circuit as described above is provided with a switching control circuit switching an external FET between an ON state and an OFF state. As the switching control circuit, for example, a circuit formed by combining an N-channel MOS (Metal Oxide Semiconductor) transistor with a P-channel MOS transistor is employed.
When an FET driving IC (Integrated Circuit) in which FET driving circuits are integrated has an abnormality such as a short circuit of an external terminal, there may be a case where control is performed to turn off an external FET by turning on one of the N-channel MOS transistor and the P-channel MOS transistor in the switching control circuit and turning off the other thereof, in order to prevent a large current from flowing into the external FET and breaking down the external FET or a circuit at the next stage of the external FET.
However, when a short circuit occurs between a ground potential, a power supply potential, or the like and an external terminal to which an output of the switching control circuit is connected, although the external FET can be turned off, a large current may flow into the MOS transistor in an ON state in the switching control circuit, and break down the MOS transistor.
To solve such a problem, there can be conceived a structure that turns off both of the N-channel MOS transistor and the P-channel MOS transistor in the switching control circuit when an abnormality occurs, and includes a pull-down resistor or a pull-up resistor supplying a gate of the external FET with a bias voltage turning off the external FET. In such a structure, however, due to a parasitic capacitance of the external FET and the pull-up resistor or the pull-down resistor generally having a value of several tens of kilo-ohms, a longer time is required to cause transition of a potential at the gate of the external FET from a potential corresponding to the ON state to a potential corresponding to the OFF state, which may break down the external FET or the circuit at the next stage of the external FET.